The scaling of VLSI circuits is a constant effort. With circuits becoming smaller and faster, improvement in device drive current is becoming more important. When device dimensions are reduced to 130 nm and lower, particularly 65 nm and lower, conventional methods for improving device drive current, such as shortening gate length and increasing gate capacitance, become difficult to implement. Further methods such as increasing carrier mobility have thus been explored.
Among efforts made to enhance carrier mobility, forming a stressed silicon channel is a known practice. Stress, sometimes referred to as strain, can enhance electron and hole mobility. The performance of a metal-oxide-semiconductor (MOS) device can be enhanced through a stressed-surface channel. This technique allows performance to be improved at a constant gate length, without adding complexity to circuit fabrication or design.
Typically, it is preferred for NMOS devices to have tensile stresses in their channel regions, while it is preferable for PMOS devices to have compressive stresses in their channel regions. Stresses in channel regions can be applied by forming stressed source/drain regions, stressed gate electrodes, stressed contact etch stop layers, etc. One of the methods for applying a tensile stress to a gate electrode of an NMOS device is to form a stress memorization layer, wherein a typical formation process includes blanket forming a stress memorization layer having an inherent stress, performing an annealing, and then removing the stress memorization layer. A tensile stress is thus “memorized” by the gate electrode, and is imparted to the channel region of the NMOS device.